A semiconductor memory device is usually used to provide data storage for a microprocessor. Historically, semiconductor memory devices have been controlled asynchronously by the processor. That is, a microprocessor typically applies addresses to inputs of a memory device and strobes them by using the RAS (row address strobe) and CAS (column address strobe) pins. The addresses are held for a required minimum length of time. During this time the memory device accesses its addressed locations and after a maximum delay either writes new data from the processor into its locations or provides data from the locations to its outputs for the processor to read. During this time, the processor must wait for the memory device to perform various internal functions such as precharging the lines, decoding the addresses, sensing the data, and routing the data out through the output buffers. This creates a "wait state" during which the high speed processor is waiting for the memory device to respond, thereby slowing down the entire system.
Calculation speeds in processors have improved. As a result, there is an increasing demand for semiconductor memory devices with increased access speed. However, the process technologies presently available and the relatively large chip sizes of ultra large scale integration circuits limit the access speeds of memory devices.
To improve the bandwidth of semiconductor memories, several architectures have been used. One common approach is the synchronous interface architecture. Making memories synchronous puts them under the control of the system clock. Synchronous memories use input and output latches for holding the memory data. Input latches can store the addresses, data, and control signals on the inputs of a memory device. After a preset number of clock cycles, the data can be available on the output latches of the memory device with synchronous control for a read from the memory or a write to the memory. Synchronous control means that the memory device latches information from the processor in and out under the control of the system clock. Since the number of clock cycles required for the memory to complete its task is predetermined, the processor can safely perform other tasks while the memory is processing its requests. A major advantage of synchronous control is that the system clock edge is the only timing strobe that must be provided by the system to the memory. This reduces the need to propagate multiple timing strobes around the printed circuit board or module.
While memory devices are making significant gains in speed and bandwidth, there still remains a gap in the speed requirements of the processors. The solution for providing adequate memory bandwidth depends on the system architecture, the application requirements and the processor, all of which help determine the memory type to be used in a particular application.
An approach for increasing the speed and the bandwidth is the burst access technique. The burst access allows the internal timing delay components to be decreased. According to this technique, for example, active read/write command and precharge time can be hidden after the first access. In a burst memory, following an initial address input, subsequent addresses are internally generated in rapid succession without inputting new address information to the burst memory. Thus, a series of burst data words currently on the sense amplifiers can be clocked out rapidly following the access of the first data word. These burst mode accesses take advantage of the fact that the internal bus of the memory device is wider than the external bus. This permits all of the data from a series of burst mode addresses to be fetched from the burst memory device to its outputs upon the entry of the initial address.
Another approach for increasing the speed and the bandwidth is described in a paper from "Symposium on VLSI Circuit Digest of Technical Papers," published in June, 1992, pages 66-67, by Kushiyama, N., et al., entitled, "500 Mbyte/sec Data Rate 512 Kbits.times.9 DRAM Using a Novel I/O Interface." The synchronous memory device described therein accesses data in response to both rising and falling edges of an external clock signal, thus doubling the data rate of the memory device. The double data rate memory overcomes the limitation of a single data rate memory. During a double data rate read operation of the memory device, addresses are registered at the first rising edge of external clock, and the internal array latches data of twice the external data length. During the next cycle, data are driven to the external data bus sequentially on both rising and falling clock edges.
To assure input/output synchronization, many double data rate memories use complementary input/output strobe clocks synchronized with the data output. See, for example, U.S. Pat. No. 5,513,327, entitled, "Integrated Circuit I/O Using A High Performance Bus Interface," issued to Farmwald et al. on Apr. 30, 1996 and ISSCC Digest of Technical Papers, pages 378-379, February, 1996, entitled, "A 32-Bank 1Gb DRAM with 1GB/s Bandwidth," by Yoo, J. H., et al.
The conventional input/output data strobe clock generation schemes, however, may not adapt to the transition between the single and double data rate modes and the variation of the burst length during the time that a burst read or write operation is being performed.